The invention relates to the field of clock generators for electronic circuits. In particular, the invention deals with a clock circuit for generating two clock signals that are phase shifted and in which either the positive or the negative parts of the signals do not overlap.
Digital electronic circuits typically require one or more clock signals to maintain the timing of signals through the circuit. In the case of a shift register, such as the one illustrated in FIG. 1, latches are commonly connected in series and data is shifted through from one latch to the next. As can be seen from FIG. 1, the shift register circuit 100 has two latches (or flip-flops )102, 104 each with its own clock input CLK1112, and CLK2114, respectively, which shift data through the latches. The data, Din on input line 116 is shifted through the latch 102 when CLK1112 is high to emerge after a certain time delay as Dint, and shifts through latch 104 when CLK2114 is high to emerge after some time delay from the second latch 104 as Dout. This is represented in FIG. 2 by the timing diagrams. At time t1 the first clock CLK1112 goes high causing data sitting on Din line 116 to shift to the output of latch 102 as shown by the Dint signal in FIG. 2 changing from data1 to data2. When CLK2 goes high at time t2 the data at the input to latch 104 is shifted through to its output. Thus data2 at Dint shifts through to Dout.at time t2.
In practice, however, circuits include parasitic capacitance and resistance, which is depicted in FIG. 3 by capacitor 300 and resistor 306. This causes a time delay in the clock signal CLK2, resulting in a delayed clock CLK2xe2x80x2 to the latch 304. This can have severe consequences in the propagation of the data through the shift register, as shown in the timing diagrams in FIG. 4. As before, data Din is shifted through the first latch 302 at time t1. However, now CLK2 is delayed and appears as CLK2xe2x80x2 which thus remains high till after the transition of CLK1 going high. As a result, data2, which has been shifted through to the output of latch 302 at t1, continues to be shifted through latch 304 since latch 302 is still being presented by a high clock signal from the delayed clock pulse. Thus, immediately after t1, the data appearing at the output Dout is data2 instead of data1, because CLK2 has been skewed. One approach to avoiding the above condition is to provide for non-overlapping clock signals. A prior art non-overlap clock generator is shown in FIG. 5. Two cross-couple NAND gates 500, 502 are connected to a clock input signal (clock) 504 and are provided with delay lines 510, 512, respectively to generate two non-overlap clock signals, CLK1, CLK2 at outputs 520, 522, respectively. An inverter 530 ensures two different phases for the two clock signals, while the delay lines and propagation delays through the NAND gates ensure non-overlap, as will become clearer from the timing diagrams of FIG. 6. For ease of understanding, letters have been added to FIG. 5 and timing diagrams are provided for these various sections of the circuit. The clock input signal (clock) 504 is inverted by inverter 530 as shown by the signal A. After a short time delay caused by the propagation delay through the NAND gate 500, the negative output of the NAND gate 500 toggles as shown by the signal B. This output signal from NAND gate 500 is fed to the input of NAND gate 502 via a resistance path or delay line 512 to result in a delayed version of the signal B, delayed by a time d1 as shown by signal C. The positive signal together with the positive clock input results in a low signal at the output of the NAND gate 502, and is delayed through the NAND gate 502 by a time d2 as shown by signal D. This signal is, in turn fed back to an input of the NAND gate 500 via a delay line 510, resulting in a delay in the signal as indicated by signal E. The CLK1 output goes low when either or both of the inputs to the NAND gate 500 are low. This happens when the positive pulse of the clock input signal is inverted by the inverter 530. Thus, taking the clock input going high as the starting point, after a delay determined by the inverter 530, NAND gate 500 and inverter 534, CLK1 goes low. For CLK2 to go high, both inputs to NAND gate 502 must be high. The clock input is high but C is delayed by the signal moving through the inverter 530, NAND gate 500 and delay line 512. As shown by the delay d1, the delay at C is caused largely by the delay line 512. CLK2 then goes high after an additional delay through the NAND gate 502 and inverter 532. Thus CLK 2 going high is delayed for some time after CLK1 went low. CLK2 again goes low due to either input of NAND gate 502 going low. Most importantly, though, CLK1 must not go high until after CLK2 has gone low. This is ensured by the time delay d3. For CLK1 to go high, both inputs to NAND gate 500 must be high. Thus the clock input going low is not enough. Input E also has to go high. Since input E emanates from output D of NAND gate 502 and is fed through the delay line 510, the delay line ensures that CLK 1 will not go high before CLK 2 has gone low.
Thus the delay lines 510, 512 are critical to the functioning of the circuit. If they are chosen too small, the clock skew may so great as to cause malfunction of the system. If they are chosen too large, the active states (or cycle time) of CLK1 and CLK2 will be decreased substantially. This requires the periods of the clock signals CLK1 and CLK2 to be increased to ensure that the active period remains long enough, which, in turn slows down the signals and degrades the performance of the circuit.
One prior art circuit makes use of NAND or NOR gates to produce the two output clock signals and a selectable number of inverters as the delay elements in the circuit. However, even the slowest standard library inverter cells do not have much delay. Furthermore, it is not necessary or useful to have that type of resolution in tuning the non-overlap time. Also, if the inverters are not standard elements, one would have to do SPICE simulations to characterize the circuit over all process corners, temperatures and supply variations.
Another prior art circuit makes use of a depletion mode device for producing one clock output and connecting the input and output of the device to a NOR gate to produce the other clock output. However, this requires the use of special depletion mode devices, which are not readily available when using standard processes.
The present invention provides a non-overlap clock generator circuit using standard library components which are fully characterized. The resolution of the non-overlap delay is in the order of clock-to-Q delay of a flip-flop, which provides sufficient non-overlap time without cutting too much into the cycle time.
The invention provides a non-overlap clock circuit that uses programmable delay circuits in the form of flip-flops for ensuring that either the low or the high portions of the output clock signals do not overlap.
According to the invention there is provided a non-overlap clock circuit, comprising a first flip-flop providing a first clock output from its non-inverted output, a second flip-flop providing a second clock output from it inverted output, wherein the first flip-flop and second flip-flop are triggered by a common input clock signal and are set up to toggle in response to the input clock signal, a first feedback loop from the first clock output to control the triggering of the second flip-flop, and a second feedback loop from the second clock output to control the triggering of the first flip-flop, wherein the first and second feedback loops include programmable delay circuits. Each programmable delay circuit may include a set of flip-flops defining a delay path, with the output of each previous flip-flop feeding the clock input of the next flip-flop, each flip-flop introducing a propagation delay through the flip-flop, wherein any number of the flip-flops can be selected for inclusion in the delay path. The outputs of the flip-flops are typically connected together using transmission gates, wherein the flip-flops are selected for inclusion in the delay path by selecting the corresponding transmission gates using control logic. The non-overlap circuit may include an edge detector providing the common input clock.
Further, according to the invention, there is provided a non-overlap clock circuit that provides a first and a second clock signal in which either the low or high portions of the signals do not overlap, the circuit including programmable delay circuits for delaying the transition of a first signal to a first state for some time after the second signal has gone to the second state, and delaying the transition of the second signal to the first state for some time after the first signal has gone to the second state, wherein each programmable delay circuit includes a set of flip-flops defining a delay path, with the output of each previous flip-flop feeding the clock input of the next flip-flop, each flip-flop introducing a propagation delay through the flip-flop, wherein any number of the flip-flops can be selected for inclusion in the delay path.